1. Field of the Invention
This invention relates to the field of integrated circuits and, more particularly, to high impedance states programmably formed on select input/output pads of an integrated circuit.
2. Description of the Relevant Art
Complimentary metal-oxide-semiconductor (CMOS) has become popular when used in low power integrated circuit devices. A CMOS device includes both p-channel (PMOS) and n-channel (NMOS) transistors, wherein current is designed to flow from the source terminal to the drain terminal of the transistor when the voltage upon a gate conductor exceeds a threshold amount. Current flows in a PMOS transistor when gate voltage is lower than the voltage upon the source terminal. Current flows in an NMOS transistor when gate voltage is higher than the voltage upon the source terminal.
In order to retain the low power advantages of a CMOS device, it is important to ensure the gate terminal voltage not be allowed to float during periods of non-use. If the gate terminal voltage is left to float between, e.g., a power supply and ground, then that device as well as possibly other connected devices may turn on thereby causing momentary shorting of the power supply. This problem becomes readily apparent at the electrical interface lines between integrated circuits employing CMOS devices.
CMOS integrated circuits, and integrated circuits fabricated in other semiconductor technologies, interface to one another using buses. Signals upon the buses are activated and deactivated according to a predetermined protocol. Circuits employing the protocol are embodied on each integrated circuit, wherein the circuits are bus interconnected. Signals upon the bus may be classified with respect to a particular integrated circuit as input and/or output signals. Input signals are received by an integrated circuit; output signals are conveyed by the integrated circuit; and input and output (input/output signals or bi-directional signals) may be an input signal during one clock cycle and an output signal during another clock cycle. The protocol employed by the integrated circuit determines whether an input/output signal is an input or an output signal during a clock cycle. It is noted that a signal is activated when it conveys a value indicative of a certain item of information, and deactivated when it conveys a value which is not indicative of the certain item of information. A signal may be activated when it conveys a logical zero value or, conversely, when it conveys a logical one value. It is further noted that the term "clock cycle", as used herein, refers to the period of a clock signal coupled to the integrated circuit. The clock signal defines times at which memory elements (such as registers) capture a value from their inputs. The value is stored by the memory element during the next clock cycle. Combinatorial logic coupled between memory elements calculates the new value to be captured by each memory element during the clock cycle.
Input/output signals often may be idle during certain clock cycles (i.e. no integrated circuit is conveying a value upon the bus during that clock cycle). During such clock cycles, the conductors upon which the input/output signals are conveyed may be floating; namely, the conductors are not being driven to a defined logic one or zero voltage level. The gate terminal of a CMOS transistor which receives a conductor having a floating value signal will draw unacceptably large amounts of power. CMOS devices draw the least amount of power when their inputs are at the upper supply level (i.e., VDD or VCC power level) or at ground voltage level. If the gate terminals of those devices are allowed to float between power and ground, then significantly larger amounts of power will be consumed. Often, system designers install pullup or pulldown resistors at the input/output pads of an integrated circuit to prevent input/output pads from floating. Instead, a power supply or ground voltage level is applied to the pads during times in which the conductors are presently not in use. Unfortunately, these resistors increase overall system cost.
It would be desirable for an integrated circuit to be programmably configurable. More specifically, there would be advantages to design an integrated circuit having a feature for programmably connecting a path between a non-used input/output pad and power (or ground) voltages. The programmable feature would include a mechanism for selectively activating a pullup or pulldown resistor connectable to the input/output pad of an interface conductor. The interface conductor extends from the input/output pad of one integrated circuit to an input/output pad of another integrated circuit. As such, a programmably active pullup device on one integrated circuit ensures the gate terminal of a PMOS device of another integrated circuit, connected to the active pullup via an interface bus conductor, is turned completely off and does not consume power when not in use. Further, a programmably active pulldown resistor on one integrated circuit ensures the connected gate terminal of a non-used NMOS device of another integrated circuit is turned completely off. The programmable device must be one capable of reconfiguring pullup and pulldown features of select input/output pads depending upon the state of those pads. For example, if an active signal is forwarded across a pad during one clock cycle and an inactive signal is sent in a subsequent cycle, the associated pad must not be configured with a pullup or pulldown in the initial cycle but must be configured (either with a pullup or with a pulldown) during the next cycle. Selection of how and when to configure a pad presents numerous problems which must be overcome before programmability of pullup and pulldown can be achieved.